In integrated circuit manufacturing processes, layouts of integrated circuits are designed, often in a graphic data system (GDS or GDSII) format. After the design is finished, the integrated circuits are taped-out to be manufactured on silicon wafers.
Generally, the tape-out of integrated circuits involves a high cost, typically ranging from hundreds of thousands of dollar to a million dollars. If the first tape-out is not successful and issues are found, iterations are needed to redesign the integrated circuits and to tape-out the integrated circuits again. The design cost is thus increased. Further, the time-to-market becomes significantly longer. Therefore, it is important to achieve success in the first tape-out (first silicon success).
To ensure the first silicon success, various methods were used to check the correctness of integrated circuit design. U.S. Pat. No. 6,078,737 describes a method for performing design-rule checks on layouts of integrated circuits, wherein the geometry of polygons in the layouts is checked to ensure that the geometry of the polygons do not violate any design rule required by manufacturing processes. The polygons are the shapes of the components in the integrated circuits. For example, the width of the polygons may be checked to ensure the minimum width requirement of features can be met.
U.S. Pat. No. 5,903,469 describes a method for performing a layout-versus-schematic check, wherein device (the assembly of polygons) types, dimensions, and interconnections are checked by comparing the layout of a design (in GDS format) and the schematic (in Netlist format) of the design.
U.S. Pat. No. 6,735,749 describes a method for performing a design-rule check or an electrical-rule check, wherein specific connections of circuits are checked. For example, some of the nodes cannot be connected to power, but can be connected to ground. Therefore, the check is performed to ensure these nodes are not connected to power.
The methods described in the above-recited patents, however, cannot guarantee the first silicon success. It is observed that all three methods are related to the checking of the layout geometry of libraries and intellectual properties (IP), while the application and usage correctness of libraries and IP(s) cannot be checked. In other words, the above-recited patents only describe the checking of the correctness in the design and layout of libraries and IP(s), while the correctness in the use of libraries & IP(s), which are related not only to libraries and/or IPs themselves, but also to the interactions between library and library, library and IP, and IP and IP, is not checked. Further, some of the libraries and IP(s) may have specific requirements. Taking an I/O library as an example, a particular standard I/O cell cannot adjoin certain other types of standard I/O cells. These cell-specific requirements also cannot be enforced by the methods described in the above-recited patents.
Conventionally, the application rules, which specify how a library or IP should be used, were only specified in documents known as application notes. The application-rule checks were manually performed by the library/IP users (i.e., designers), who inspect the integrated circuit layout to ensure that the application rules specified in the application notes are enforced. However, the application notes often include hundreds of pages. It is extremely difficult for users of the libraries and IP(s) to comprehend all application rules specified in the application notes. Further, as process technology continuously evolves forward, more and more application rules are needed, leading to a drastic increase in the usage complexity of the libraries and IP(s). As such, the problems caused by the misuse of the libraries and IP(s) will further increase, and a chance to achieve the first silicon success lessens.